A method for sealing bonding pads of integrated circuits by a passivation layer is known from the publication U.S. Pat. No. 5,136,364. A structured passivation layer is applied in such a way that it overlaps the edges of the bonding pad. Such a method is relatively time-intensive and cost-intensive, since it requires the structured production of the passivation layer. Moreover, the US publication does not disclose the production of electroceramic components by the method discussed there.